Code conversion system



Nov. 28, 1961 A. M. ANGEL ET AL CODE CONVERSION SYSTEM 6 Sheets-Sheet l Filed NOV. l, 1957 Nov. 28, 1961 A. M. ANGEL ET AL 3,011,165

CODE CONVERSION SYSTEM Filed NOV. l, 195'? 6 Sheets-Sheet 2 NOV- 28, 1961 A. M. ANGEL ET AL com: CONVERSION SYSTEM e sheets-sheet 5 Filed Nov. l, 1957 NQQQNNN @M mw@ NOV- 28, 1961 A. M. ANGEL ET AL 3,011,165

CODE CONVERSION SYSTEM Filed Nov. l, 1957 6 Sheets-Sheet 4 Nov. 28, 1961 A. M. ANGEL ET AL CODE CONVERSION SYSTEM 6 Sheets-Sheet 5 Filed Nov. l, 1957 who Wm j

Nov. 28, 1961 A. M. ANGEL ET AL CODE CONVERSION SYSTEM Filed Nov. l, 1957 6 Sheets-Sheet 6 600 zal 600 nel( m. 55ml,

,J//arnega nite i 3,911,165 CODE CONVERSEGN SYSTEM Arthur M. Angel, Rolling Hills, and Robert Brahman,

Gardena, Calif., assignors to The l Tational Cash Registe Company, Dayton, Gino, a corporation of Maryland Filed Nov. 1, 195?, Ser. 693,871 8 Claims. (Cl. Seti-347) This invention relates to code conversion apparatus and more particularly to an improved conversion matrix utilizing magnetic cores for converting information encoded in any one of a plurality of input codes to a desired output code.

In the computer art, characters represented in various binary codes, as stored on punched tape, for example, may be required to be read and converted into a common code to be operated upon in a central data processor. One of the problems in conversion of characters from one code to another is that various storage codes, as read from the tape, may vary greatly from each other as, for example, by having different numbers of binary bits in dilerent codes to represent characters or by having some codes utilizing a separate character to determine whether subsequent stored characters are upper case or lower case in form.

in the prior art, diode matrices have been employed for converting characters represented in au input code into an output code to be used, for example, in a central data processor. in one arrangement, the binary signals representing characters of an input code are passed into a diode matrix which decodes the binary signals to thereby select a certain line, for each input character, on which to pass a signal. After this selection, the signal passes on this selected line to an encoding matrix comprising diodes arranged so the signal causes binary output signals to be formed on output lines, which output signals represent the desired characters in the output code. One disadvantage of this arrangement is that a large number of diodes are required, and also that a large amount of current is required by these diodes. Also when a plurality of input codes are to be converted to an output code, gating arrangements which result in an increased number of components are required.

An object of this invention is to provide a code conversion system for converting information represented in one of a plurality of input codes to information represented in a common output code, in an improved and simplitied manner, by the utilization of magnetic cores.

Another object of this invention is to provide a code conversion system which is economical in the employ of diode components and overall component requirements, and from the viewpoint of power dissipation requirements.

Another object oi this invention is to provide a code conversion system which forms a parity check bit in a sirnplied manner with a minimum of additional components.

Another object of this invention is to provide a. code conversion system which decodes a character represented in an input code as a result of selection of a magnetic core to be driven to its opposite magnetic state, and encodes the character into an output code as a result of the presence or absence of sense lines wound through the selected core.

A further object of this invention is to provide an improved arrangement for obtaining output pulses in response to signals provided by cores changing state Briefly, the code conversion system of this invention comprises a matrix of magnetic cores, individual cores of which are selected by decoding networks responding to combinations of binary signals representing input characters in various input codes. For each core corresponding to an input code, a unique set of sense lines is provided, with one sense line connected to each sense amplifier of a unique set of sense ampliers for that code. The outputs of corresponding sense ampliiiers of al1 sets are connected in common to corresponding lines of a set of output lines. Thus desired combinations of the presence or absence of the sense lines for each input code are wound through each cor., representing characters in that code, so that selection of each core causes signals to be formed on certain sense lines. These signals activate desired combinations of the sense amplifiers to form true output signals on desired output lines, thus forming coded output signals. Therefore, decoding of the input characters is carried out by selecting cores, and encoding to form the output character is carried out by activating desired combinations of sense ampliers as a result of the combinations or the presence or absence of sense lines wound through the selected cores. Switches are provided with certain ones being closed in order to change the decoding networks for the different input codes, Le., 5, 6, 7, or tl bit codes, and to select the dill-arent sets of sense anipliers to be used for the different input codes. Although in each input code a unique core is selected for each irput character by the decoding networks, where sirnilabinary combinations of signals are utilized to represent characters in more than one of the input codes, thevsame core is selecte for decoding the characters in each of these input codes. A core selected by more than one of the input codes is wound with a desired combination of the presence and the absence of sense lines required for each input code. Thus the binary output signals representing the output characters are formed for each input code, as selected by the previously mentioned switches. Also, binary output signals representing parity check bits are formed along with the signals representing the output characters. A novel circuit arrangement is utilized to form the binary output signals by delaying at the sense ainpliiier, the signal sensed as the result of the magnetic core changing state.

Further objects and advantages of the invention will be apparent to those skilled in the art from the following drawings and descriptions in which:

PEG. l is a block diagram of the code conversion system of this invention.

PEG. 2 is a schematic diagram of the core matrix and of the decoding networks for selecting the column and row drive lines.

FIG. 3 is a table showing the binary states of the input codes, the cores selected for decoding these input codes and the binary states of the output code.

FIG. 4 is a circuit diagram of the core matrix of this invention to explain the arrangement of the cores utilized in this embodiment.

FlG. 5 is a circuit diagram to explain the arrangement of the sense ampliiiers and the sense amplifier bias circuit.

FIG. 6 is a detailed circuit diagram of a portion of the core matrix of FIG. 4 to explain the arrangement of the sense lines.

FIG. 7 is a schematic diagram of the logical input network of dip-flop A1.

FIG. 8 is a schematic diagram of the waveforms to explain the operation of the circuits.

FiG. 9 is a schematic diagram of the magnetic characteristics of the cores for explaining the core biasing and driving arrangement.

lecrring iirst to l, a block diagram is shown of the code conversion system of this invention showing 'ne input lines which carry coded input signals received trom tape reading circuitry, for example, and the output nnesrwhich carry coded output als to the central Vknown in the art.

`lines lem and lau, respectively.

data processor. Core matrix 22 comprises cores aS tid-i arranged so as to be wound with column drive lines as and row drive lines as -il5. Decoding of an input character represented by coded input signals in codes F, D, or T is carried out by selection of a column and a row drive line, as C-tii and lic-tid, respectively, to select and drive a core, as will be explained subsequently. 'l`he coded input signals, as l1, l2, i3, etc., and clock signal Cl are signals received from reading t eads for punched tape comprising photodiodes, and passed through pulse forming and amplifying circuitry (not shown). The primes of the input signals, as i1', l2', I3', etc., which are required ink order to deco-de the binary combinations, are signals received from the reading head for punched tape and inverted in the pulse forming and amplifying circuitry. Column drive lines as C-iltl are selected by decoding network 26 acting through diode connections Sil to select a plurality of lines, one line as C-iit'r in each of four groups of lines, which groups are selected by decoding network 27. Row drive lines as lil-@5' are selected by decoding network 23 acting through diode connections 35 to select a plurality of lines, one line as R-il in each of four groups of lines, which groups are selected by decoding network 29. The inputs to decoding networks through 29 are the coded signals on lines l1, l1', l2, etc., as received from tape reading circuitry, representing the coded input characters, and the clock signal on line C1. For converting the ditierent input codes, switches S1 and S2 which control decoding network 2? and switches S3, Si, and S5 which control decoding network 26 are set at desired contigurations of being opened and closed for each input code F, D, and T, as will be explained subsequently. After a core is slected, i.e., the coded input signals as Il, il', l2, etc., representing an input character are decoded, current pulses in response to clock signal C1 are passed in coincidence through the selected column drive line and row drive line wound through the selected coro to overcome a bias current passed through the cores. Thus the selected core is driven to its opposite state of magnetic rlux. The bias current is supplied by a core biasing arrangement which passes current from ground 3l through line d5', through each of the cores of the matrix and thence to l2 volt terminal 32, as will also be explained subsequently.

For encoding the input character as determined by the core selected in each nut code, desired sense lines as im of the set of sense rines im through iTn are wound through each core as Ctrl-@5, the presence of each sense line in a selected core resulting in a true signal on the sense line when the core is driven to its opposite magnetic state. All sense lines as im, im, lm, for encoding input codes F, D, and T, respectively, connect `from 2G volt terminal 52 through the cores, as titl-d5, to sense amplilier circuits, as 4l, to form output signals on output lines as im in response to signals on the sense lines. The signals on output lines im through 11:6 represent the output character the processor code and the signal on output line PT represents the parity check bit accompanying the output character, as will be explained subsequently. The signal on output line lpg controlled by sense line IFS connected to sense amplirer circuit di? is used to distinguish charactes represented by the same binary combinations in the processor code as will also be explained subsequently. A parity generator S5 forms an error halt signal in response toan error as determined bythe signals on output lines im through IE7, as well @ther sense lines as im connect to sense amplifier circuits di) to form control signal lag which passes to clock inhibit circuitry (not shown) to control receivinrr of characters by the central processor. Also, other sense lines as 1F10 and EFH connect to sense amplier circuits and 5ft to form control signals on Flip-flop Al which is triggered by clock signal C2, which signal is clock signal C1 delayed in delay circuit 25' as will be explained subsequently, has its outputs A1 and A1 connected to decoding network 26 to control selection of cores for encoding upper or lower case output characters for certain input codes. A bias circuit 59 for the sense arnpliiiers is controlled by switches S11, S13, and S15, one oi which is selected and closed for each of the input codes to be converted to the output code in order to select a sense amplifier of each sense amplifier circuit, as 4l.

Referring now to FlG. 2, a detailed schematic diagram is shown of a portion of the code conversion system of Pif. l showing the column and row drive lines of the core matrix and the decoding networks for electing the column and row drive lines. As discussed, column drive lines as C-ilt are selected -by decoding networks 26 and 7 and row drive lines as R-llS are selected by decoding networks 2S and 29. To explain the decoding networks, refer also to PEG. 3 which is a table showing the binary states of characters represented in the input codes and the output code. rl^he three input codes for this ernbcdiment, codes F, D, and T, are comprised or" six, seven, and tive binary bits per character respectively. These codes are typical codes which may be used in storing characters on punched tape, for example. lt is to be understood that the characters shown are to illustrate the features of this invention and additional characters may be utilized in a similar manner in each code. To select a core as dll-it, for example, which is selected to be driven to its opposite magnetic state for decoding the character l in code D, switches S2 and S3 are first closed by relays (not shown). it is to be noted that cores are designated by columns and rows as core tl$-d5 located column C-iti and row R-iid. Closing switch S2 ccnuects the emitters of transistors and 76, which are of the p-n-p type, to ground 57, which transistors are controlled by input signals l5 and I6', respectively, connected to their bases. Closing switch S3 connects the emitters of transistors '7l and 72, which are of the p-n-p type, to ground 7d, which transistors are controlled by input signals lq and lq, respectively, connected to their bases. Thus, as will be explained, the seven binary input signais representing the character l in code D can be decoded to select column and row drive lines as C-iiil and lic-it, respectively. It is to be noted that the logical voltage levels for this embodiment are ground and 8 volts for true and false signals, respectively, with a true signal representing a binary one and a false signal representing a binary zero. As seen in FiG. 3 for the character l in code D, input signals i3 and lr are false. Therefore, transistors @il and 3g, which are of the n-p-n type, are biased into a conductive state by the signals on lines I3 and I4 which are connected to the oase of transistors 38 and S9, respectively. Since signals i and lr are at a high potential, the group of column drive lines comprising drive line C-il'll is selected. Also since signal i7 is false, transistor '72, which is of the p-n-p type, is biased into a conductive state as a result of the low potential of signal i7 applied to its base to select line C-ll of the group selected by decoding network 27. Thus, when transistor which is of the n-p-n type, is biased into conduction by a positive clock signal C1 applied to its base, a current pulse passes from ground '74 through transistor 72, through current limiting resistor 39, through drive line C-tld, through transistors SS, 39, and 9d and through inductor @e to 8 volt terminal 9i. Also, for the character l in code D, input signal l1 is true and I2 is false. Therefore, Vtransistors 77 and 7&5, which are of the n-p-n type, are biased into a conductive state by signals l1 and l2', resL ectively, applied to their bases at a high potential, to select the group ol' row drive lines comprising line R-GS. Since input signal l5 is true and le is false, transistor ed, which is of the p-n-p type, is biased into a conductive state by signal 15 applied to its base at a low potential; and transistor 75, which is of the p-n-p type, is biased into a conductive state by signal i6 applied to its base at a low potential. Thus drive line ll-tl is selected in the group selected by decoding network 29. Therefore, when transistor 79, which is of the n-pn type, is biased into conduction by a positive clock signal C1, a current pulse is passed from ground 67 through transistors 75 and 66 through current limiting resistor 3S, through drive line R-'il5, through transistors 77, 73, and. 79 and through inductor 97 to 8 volt terminal 9i in coincidence with the current pulse passed through drive line C-dtl. Transistors 92 and 93 which are of the pn-p type, are biased into conduction when clock signal C1 is at a low potential to maintain a current from ground potential through inductors he and 97 at all times when transistors 90 and 79, respectively, are biased out of conduction. Thus, when transistors 93 and 79 are biased into conduction by clock signal C1, inductors 96 and 97 act to resist changes of current through the drive lines caused by the back electromotive force induced by cores changing state, to maintain a driving current pulse of constant amplitude through the cores. T he current driving pulses 57 and SS (FG. 8) of constant amplitude causes the signals on sense lines resulting from a core changing state to have a large amplitude and thus to give more reliable signals out of the sense amplifiers, as will be explained subsequently.

For selection of cores in code F, switches S2 and Si are closed for conversion of this input code comprising six bits per character. Closing switch S2 connects the emitters of transistors i5 and 76 to ground 67, which transistors are controlled by signals l and le', respecively, connected to their bases so as to include input signals l5 and ls in the decoding. Closing switch S connects the emitter' of transistors Idil and lill to ground 74 so that when either output signal A1 or A1, respectively, of dip-flop Al is at low potential, one transistor or the other will conduct. Core uti-l5 which represents the character A in code F is selected in a similar manner in code F as explained for the selection of the same core @tl-(l5 in code D, which core @rtl-d5 repre` sents the character i in code D. A feature of code F is that it has an upper a lower shift input character that is decoded by selectinfr cores which cause control signals i010 and i011 to be formed at a high logical potential to determine whether subsequent input characters are upper or lower shift. The control signals i010 and ICM set flip-flop A1 (FlG. l) as either true or false, and the outputs act lto select certain columns of drive lines. Input characters following an upper and a lower shift input character are encoded into lower and upper Case output characters, respectively, in the processor code, as will be discussed subsequently.

For selection of cores in codc T, switches S1 and S4 are closed for the tive bit re resentation of the input characters. Thus it should now be clear that by leavJ ing switch S2 open, transistors, as 75, controlled by signal ls connected to its base, are eliminated from the decoding. By closing switch Si, transistors lut) and lill are connected to ground 74 so that signals A1 or A1 rom hip-flop A1 will select cores for decoding upper or lower shift characters. lt is to be noted that column drive lines are selected by the binary input signals i3, l1, I1, and I8 and their primes, while row drive lines are selected by the binary input signals l1, l2, l5, and l5 and their primes. This arrangement allows the desired selection of both columns and rows for input characters represented by only five bits, as well as by seven bits, for example. lt is to be also noted that the decoding arrangement of the circuit of the present invention allows substitution for core matrix 22 of core matrices arranged for other input codes than those illustrated in the preferred embodiment, as will be explained in more detail subsequently. Although input code D of this embodiment is comprised of only seven bits, decoding network t5 26 provides for decoding eight binary bits by closing switch S5. Thus the arrangement of the binary inputs to decoding networks 26 through 29 for selection of column and row drive lines allows decoding, with a suitable core matrix, of an input code comprised of any xed number of binary bits up through eight.

Referring now also to FIG. 8 whichl shows waveforms to explain this invention, and to FIG. 9 which shows a hysteresis loop to explain the magnetic states of the cores, the operation of the decoding and core driving arrangement of FlG. 2 will be explained in more detail. 'Die basic reading cycle during which a character is read on punched tape is from time t1 to l5. During each basic reading cycle at Vtime t1, coded input sienals 11kg and (l1 8) as required for each input code are received from punched tape reading circuitry, for example, to pass into decoding networks 25 through 29. Coded input signals l1 8 and (l1 8) which may lbe at a high or low logical level are shown at the high logical level of 0 volts by 'waveform 53. These coded inputs select a desired column and row drive line, as discussed. At time t2, clock signal C1 as shown by waveform S6 formed from the punched tape by tape reading circuitry (not shown) passes into decoding networks 27 and 29 to bias transistors 9? and 79 into conduction. Thus current pulses of +600 milliampere turns coercive force pass through the selected column `and row drive lines as shown by waveforms 57 and 5S, respectively, to coincide at the selected core, as Oil-05. A constant bias current of 600 milliampere turns coercive force passes through each core from ground 31 through line 65 to l2 volt terminal 32 as shown by waveform 61). lt is to be noted that waveforms 57, 58, and dit are illustra tive of the coercive driving force passim. through the cores and the current amplitude depends upon the number of turns that the drive lines are wound through the cores. Thus each core is maintained at bias point 37 of its characteristic hysteresis loop, as shown in FIG. 9, by this bias current except when current pulses are passed through the column and row drive lines. Only a coincidence of +600 rnilliampere turn coercive force driving pulses of a column and row drive line as shown by waveforms 57 and 58, respectively, will overcome this bias current coercive force of waveform 6i) and drive the core to its opposite magnetic state represented by point 94 of the hysteresis loop shown in FIG. 9. At time t3, the column and row drive currents of waveforms 57 and 58, respectively, fall to zero upon the fall of clock signal C1 of waveform 56, allowing the selected core to be returned to bias point 87 by the bias current coercive force of waveform 66. The signals induced on the sense lines as shown by waveform 63 resulting from a selected core being driven to its opposite magnetic state will be explained subsequently.

Referring now to FIG. 4 which shows a circuit diagram of the core matrix of the invention and also to the table of FIG. 3, the arrangement of the cores in the matrix will be further explained. The core or cores which are selected in response to the input character for each code F, D, and T are shown in the table of FIG. 3 and in the matrix of FIG. 4. In codes F and T which have an upper and a lower shift input character, i.e., have certain characters which determine whether certain subsequent binary input characters are one or another set, called upper `or lower shift characters as is well known in the art, the binary state of flip-flop A1 (FIG. l) determines whether cores representing upper or lower shift characters are selected. For example, in code F, the character A, ywhich is defined as lower shift input character, and 'the character a, which is dened as an upper shift input charac er, have the same binary inputs I1 through I6, and the binary state of .flipflop A1 determines whether core till-@5 or (M S, respectively, is selected. Referring now also to FlG. 2, when flip-flop A1 is set tmc, as a result of a previous upper shift character having been received, output A1' is at a low potential and transistor 10G is biased into a conductive state to select, in combination with the binary input signals, drive lines C-il, C-tiS, C-il9, or C-13, which pass through columns of cores representing lower case characters in the processor code. When hip-flop A1 is set false as a result of a previous lower shift input character having been received, output A1 of hip-flop A1 is at a low potential and transistor i101 is biased into .a conductive state to select, in combination with the Ibinary input signals, column drive lines C-iii, C-ii, C-di, or C-'12 which pass through columns of cores representing upper case characters in the processor code. Thus upper and lower shift input characters in code F, as characters a and A, respectively, are selected by transistors 106 and 1111 responding to the outputs of iiipiiop A1 (FIG. l). Upper and lower shift selection in code T is similar as discussed in -relation to code F. It is to be noted that `for selection of a core in code F, switches S2, and S4 are closed, `and for selection of a core in code T, switches S1 and S4 are closed.

Other characters of code F and T are used in cornmon with both upper and lower shift input characters and are represented by a combination of binary bits which are utilized in the input code -for only that character. Thus the one combination of binary input bits represents the one input character for both upper and lower shift. For example, the binary combination representing the character l in code F is only utilized for the character 1 and must therefore select a core representing 1 for either state of flip-flop A1. Thus two cores as 66434 and (i1-04 are utilized to represent the character l for conversion, so that the single binary combination of input signals will select one core or the other depending on the state of ilip-iiop A1. Therefore, selection of either core @4l-14 or {t1-04 results in decoding of the same character l. Also it is to be noted that a single core can 'be used for decoding characters in a plurality of the input codes as core (t4-04 which in code F, D, and T is selected for decoding characters 5, G, and H, respectively.

Referring now to FIG. 5 which shows a circuit diagram to explain the operation of the sense ampliiiers of FIG. l the arrangement of the sense amplifiers and the bias circuit `for the sense yampliers will be explained before explaining in detail the sense lines wound through the cores. Sense amplifier circuit 41 comprises ampli- -fier transistors 102, 105, `and 104, all of the n-p-n type, with their bases connected to sense lines IF1, 1131, and IT1, respectively. Each input code, F, D, or T, is selected by closing either switch S11, S13, or S15 to connect '20 volt terminal `1i7 to either lines 11i), '111, or 1,12 which connect to the emitters of ampliiier transistors 192, 11%3, and 164, respectively. Switches as S11, S13, and S15 may be closed by relays, for example. Each sense line as i111 connects to the base `of an ampliiier transistor as 102 by way of resistor 1113. The Ibase of transistor 162 is connected to emitter line 110 by way of capacitor 1114 so resistor 103 and capacitor 114 act to integrate a signal on sense `line TF1 for discrimination of spurious pulses on sense line TF1. The collector of amplifier transistors .1@2, 103, and 104 connects to com- -mon line 115 which in turn connects to ground 118 by way of resistor 116 and parallel capacitor 117 to form an R-C delay circuit, as will be explained subsequently. Line i115 also connects to the base of transistor 1120 which is of the n-p-n type. The emitter of transistor 12) is connected to -8 volt terminal 123 and the collector is connected to the base of transistor 126. The collector of ltransistor 12,0 is also connected to +20 volt terminal 127 by way of resistor 128 and is clamped at ground potential by appropriately poled diode 130. Transistor 1R26 which is of the n-p-n type has its collector connected to ground potential and its emitter connected -to -20 volt terminal l132 by way of resistor 133. Outfor both upper and lower shift inputs.

put line 1p1 is connected to the emitter of transistor 12S and is clamped to -8 volt terminal L3 by way of appropriately poled diode 135. In order to bias amplitier transistors as 162, 193, and 164 when unselected so as to prevent emitter to collector current leakage, -8 volt terminal 136 of 'bias circuit 59 is connected by way of resistors as resistor 6 to lines as 115i. It is to be noted that each sense ampliiier circuit 41 through 47 of FIG. l is similar to sense amplifier circuit 41 as described. Sense amplifier circuit 4% is similar to sense amplifier 41 except that only a single amplifier transistor connected to sense line IFB is required. Sense ampli-iier circuits 49, Sil and 51 are similar to sense amplifier circuit 41 except that only two amp'liiier transistors are required in each circuit for the sense lines IFB, L19; 1F10, 1110; and 1F11, IT11, respectively. When one of the switches as S11 (FIG. 5) is closed, all ampliiier transistors as 102 connected to sense lines 11.11 through IF11 are selected in ysense amplifier circuits yi1 through 51, respectively.

Now that the arrangement of the sense amplifier circuit has been explained, reference will next be made to FiG. 6 which shows a detailed circuit diagram of a portion of the core matrix of FIG. 4, for an explanation of `the -driving lines and sense lines wound through the cores. As was discussed, column drive lines as C-(ti and row drive lines as R-S cairy current pulses to overcome a core biasing current passed through core bias line `65, to drive a selected core as Gil-65 to its opposite state of magnetic iiux. Referring also back to the table of FIG. 3, core @ii-05 is selected, i.e., an input character is decoded, in response `to the input signals representing input character A in code F and input character I in code D. Encoding `of the selected core titi-d5 in code F is carried out when switch S11 is closed to select the desired transistor of the sense amplifier circuit (FIG. 5), as discussed. The binary representation of the character A in the processor code comprises signals 1121, 11:5, 1p1 represented as ones, and 1PZ, IPS, im, 11:11, and IPS represented as zeros. Therefore, in order to convert the character A in code F to the processor code, sense lines 1111, TF5, and IF', which connect to sense ampliiiers 4,1, 45, and i7 (FIG. l), respectively, are wound through core titl-0S. This arrangement `causes only the output signals 1p1, L35, and 11:1 to rise to the high logical potential when core @il-d5 is selected and driven to its opposite magnetic sta-te, thus forming the character A in the processor code.

Encoding the character I in code D is carried out when switch S13 (FiG. 5) is closed to select the desired transistors `of the sense amplifiers (FIG. l). ,The character I in ythe processor code comprises signal 1p1, 111,1, and 11:5 represented as ones and the signals 11.2, 1123, Ipq, and IPB represented as zeros. Thus sense lines ID1, Im, and i are Iwound through core titl-05 to connect to sense amplifiers 41, 44, and 45 (FIG. l), respectively. When core @ii-it is selected and driven to its opposite magnetic state for conversion from code D, a high logical voltage signal is formed on output lines 1p1, 11:4, and IP5, respectively, to yform the character i in the processor code.

Character a in input code F is decoded by selecting core 111-05. Character a in the processor code is comprised of output signals 1p1, Ip, i137, and 11:8 represented as ones. Thus sense lines 1p1, 1F11, TF7, and im are wound through core @i1-415 so that when this core is selected, signals 1p1, IP5, 11,7, and lpg are at a high potential. It is to be noted that since the binary representation 1p1 through i117 yof thecharacters A and fr are the same in the processor code, output signal IPS is required in the preferred embodiment to distinguish the characters A and a in the central processor. Cores @wud and 111-84 as discussed are both selected for decoding the character l in input code F since this one character is utilized Since the character l in the processor code is represented by signal IPI in a true state (FIG. 3), sense line IFI is wound through both cores 00204 and l-04. Thus selection of either core -04 and 011-04 for decoding the character 1 in code -F results in the character 1 -in the processor code being vformed. It is to be noted that core (l1-04 is also selected for decoding the character in code T.

For a further explanation of the winding of the sense lines, core {I4-04 is selected for decoding in all three input codes, F, D, and T, by the input signals representing characters 5, G, and H, respectively, as discussed. Core 04E-04 is wound with sense lines IFI, IF3, and IFI, so that when converting the character 5 from input code F, output signals IPI and Ipa and IPI, respectively, will be at the high logical potential to form the character 5 in the processor code. For converting the character G from input code D, core 043-04 is wound with sense lines IDI, IDI, ID3, and Im so that output signals IPI, IPI, IPS, and IP5, respectively, will be at a high logical potential to form the character G in the processor code. Also, for converting the character H from the input code T, core 04-04 is wound with sense lines ITI and IT5 so that output signals IPI and IPI, will be at the high logical potential to form the character H in the processor code. Therefore, a single core may be selected for decoding input characters in all three input codes and will carry out encoding of the decoded characters by the desired combination of the presence and absence of sense lines wound through the core for each input code. Thus signals are formed on certain sense lines as a core is driven to its opposite magnetic state, so as to bias desired sense amplifier transistors into conduction to form the combination of output signals of the character in the processor code. It is to be noted that each amplifier transistor as 102 (FIG. 5) of each sense amplifier circuit as 41 of FIG. l is controlled by only a single sense line as IFI which is Wound through all cores that are selected for decoding characters requiring output signal IPI to be at a high logical potential.

Referring now back to FIG. 5 and to the waveforms of FIG. 8, the operation of this invention will be explained in further detail by showing the time relation of the driving pulses and the output signals. Each sense line as IFI has a signal as pulse $2 of waveform 63 induced thereon when a selected core through which the sense line is wound is driven to point 94 of the characteristic hysteresis loop of the core (FIG. 9) from bias point 87 as a result of driving pulses 57 and 58 passing through the core at time t2. When the positive pulse 82 of Waveform 63 appears on sense line IFI, the signal is integrated to provide discrimination against spurious signals on sense line IFI after passing through resistor 108 and capacitor 114. The integrated signal appears on the base of transistor 102 as the positive signal shown by pulse 85 of waveform 64 to bias transistor 102 into conduction.

Transistor 120 is normally conducting at time tI from volt terminal 127 through resistor 128 to -8 volt terminal 123 as a result of base current ilowing from ground 118 through resistor 116 through the base of transistor 120 to m8 volt terminal 123. When transistor 120 is normally conducting, line 115 is maintained at a potential of -7.9 volts as shown by waveform 80. When transistor 102 is biased into current conduction as a result of the positive pulse 85 of waveform 64 from a driven core being impressed on its base shortly after time t2, capacitor 117 charges at constant rate from 7.9 volts to -20 voltsl to form the signal on line 115, as shown by waveform 80. After capacitor 117 is charged, current passing from ground 11S through resistor 116 and through transistor 102 to -20 volt terminal 107 maintains line 115 at *20 volts. When the potential of pulse 85 of waveform 64 falls, amplifier transistor 102 is biased into a non-conductivey state to stop current conduction from ground through resistor 116 and through transistor 102 to -20 volt terminal 107. Also, as the potential on line 115, asI shown by waveform 80, falls below -8 volts, a

short period after time t2, transistor 120 is biased into a non-conductive state and the potential on its collector starts to rise from approximately -8 volts toward +20 volts to be clamped at ground potential by the action of diode 130. When transistor 120 is normally conducting, transistor 126 conducts a small current so output line IPI is clamped at the low logical potential of -8 volts through clamping diode 135. When transistor 120 is not conducting, as a result of transistor 102, 103, or 104 biased into conduction, transistor 126 conducts with an internal voltage drop such that output line IPI rises to the high logical potential of ground as shown by pulse 9S of waveform 81. It is to be noted that transistor 126 is arranged in an emitter follower configuration so as to provide a low output impedance to the output signal on output line IPI.

When the potential of the positive signal on sense line IFI falls as shown by pulse 32 of waveform 63, transistor 102 is biased out of conduction and capacitor 117 discharges through resistor 116 toward ground potential with a desired R-C time constant. The potential on line during discharge is shown by waveform 80. At time t4, capacitor 117 is discharged so the potential on line 115 has risen to -7.9 volts and transistor 120 is biased back into conduction, thus effectively clamping the potential on line 115 at this voltage. The collector of transistor 120 then rises to -8 volts which is impressed on the base of transistor 126, and the current ilow through transistor 126 is reduced. Thus the potential on the output line IPI, as shown by pulse 98 of waveform 81, falls toward -8 volts where it is clamped at 8 volts by diode 135.

When the column and row drive pulses of waveforms 57 and 58, respectively, fall to zero current at time t3, the selected core returns to bias point 87 (FIG. 9) with a negative signal induced on the sense line IFI, as shown by pulse 83 of waveform 63, which signal does not bias transistor 102 into conduction. Although the positive pulse 82 of waveform 63 appeared at time t2, the positive pulse may appear at a later time as shown by dashed pulse 84 depending on the direction that sense line IFI is wound through the selected core. For this condition, the circuit acts in a similar manner as discussed in response to pulse 84 to form an output signal as shown by dashed pulse 99 of waveform 81. It is to be noted that the output signals on output lines as IPI through IPI; and ICQ through ICII as shown by pulses 98 or 99 of waveform 81 are high in potential in response to the corresponding sense line being wound through a selected core. This high potential signal corresponds to a binary one on the output. The signal on the output lines as IPI through IPB remains at the logical voltage level of -8 volts for a binary output of zero when a corresponding sense line is not wound through a selected core. Clock signal C2 which is clock signal CI delayed by delay circuit 25 (FIG. l) rises while signals ICIII and ICII of pulses 98 or 99 of waveform 81 are at their high potential. Thus Hip-flop A1 (FIG. 7) which is controlled by clock signal C2 and signals ICIII and ICII, as will be explained, is triggered to its desired state before the control output pulses ICIII and ICII have fallen in potential.

Referring now to FIGS. l and 3 and to FIG. 7 which is a schematic diagram of the logical input networks of hip-hop A1, the control arrangement of this system -will be explained. Flip-.flop A1 is internally arranged as a cross gated ilip-ilop in which the outputs are used for triggering its logical inputs, as is well known in the art. Since clock signal C2 of waveform 61 has a long time duration, this cross gated arrangement is required in order to provide reliability in the. action of the flipilop. When signal ICIO as shown by waveform 98 is true, i.e., at a high potential when clock signal C2 as shown by waveform 61 rises, ilip-tlop A1 is set true, and consequently output AI is false so as to select cores representing upper shift characters in the input codes which are encoded into lower case characters in the processor code.

as discussed previously. Also, when signal ICH is true, i.e., at a high potential, iiip-iiop Al is set false upon the rise of clock signal C2, thus selecting cores representing lower shift characters in the processor codes, as discussed. Control signals ICM, and 1G11 are formed in the true state, i.e., high in potential, when an upper shift or lower shift input character, respectively, is received by the decoding networks land decoded lby selecting a core. The cores selected for decoding the upper shift input character are either cores {l-i3 or @943 for codes F and T; and for decoding the lower shift input character, either cores (iS-09 ontw-09 for code F, and either cores lll-i3 or ifi-13 for code T. Thus the upper shift character and the lower shift character is decoded for either state of iiip-i'lop Al.

Control signal ICQ, as seen in FIG. l, passes to clock inhibit circuitry (not shown). Control signal ICQ is a true signal for decoding of the upper shift character by winding sense lines IFQ and in, through cores dt-i3 and 9943. Also, control signal log is a true signal for decoding of the lower shift character by winding sense line lpg through cores {B3-09 and @$69, and sense line TQ through cores 12-13 and EL3-i3. Thus control signal 109 passes to clock inhibit circuitry at the high logical potential when the upper or lower shift cores are selected and driven to prevent any signals being received by the processor, during the basic reading cycle when either an upper or lower shift character is decoded.

The code delete character in `code F is utilized when it is desired to delete a character punched in error in tape, as is known in the art. Control signal lcg is utilized not only with upper and lower shift input characters as discussed, but with the code delete input characters. As discussed, control signal IC9 is a clock inhibit signal which passes to the processor at the high logical potential to prevent use of a character by the central processor. Since the code delete character of input code F is utilized when both upper and lower shift characters are converted, selection of either core lZ-lS or ifi-i results in decoding of this character. Thus sense line lpg is wound through both cores y12-15 and 12a-15 to cause signal ICQ to rise to the high logical potential as a result of selection of either core. Therefore, an input character is encoded into a single output control signal L39 by winding a single sense line IFQ through the cores selected for decoding.

Referring black to FlGS. l and 3, the parity check system of this invention will be explained in detail. Output signal Im represents the parity check bit accompanying each character in the processor code, as was explained. This parity bit IPv7, which causes the binary representation 1p1 through IP', to be comprised of an odd number of ones, is `formed in each core in the selected code F, D, or T by the presence or absence of sense lines im, Im, or im, respectively. Thus the parity bit is formed by only adding an additional sense amplifier circuit and a sense line for each input code encoded. Parity generator S5' responds to the signals on output lines 1p1 through Ipq to detect an error and pass an error signal to the central processor. Therefore, an error resulting from faulty components as sense amplifier circuits between a selected core and the signals on the output lines 1p1 through im is detected by parity generator 55.

lt will be evident that in the light of the present disclosure, modifications and changes will occur to those skilled in the `art and accordingly it is not desired to limit the invention to the specific details of the exemplary illustrated embodiment other than as defined in the appended claims.

Arepresenting said information in a common output code comprising: a set of input lines; a set of output lines; a matrix of cores of magnetic material having substantially rectangular hysteresis loop characteristics; a separate set of sense lines for each input code and predetermined ones of the sets of sense lines inductively coupled to each of said cores; decoding means including a rst group of switches selectively actuable according to the input code for controlling the response of the decoding means to signals on said set of input lines to select and drive a core of said matrix to the opposite magnetic polarity, thereby providing signals on the predetermined ones of the set of sense lines coupled to the selected core; a set of amplifying means for supplying signals on said set of output lines; and means including switches selectively actuable according to the input code for controlling the response of said set of amplifying means to the signals on the predetermined ones of the set of sense lines coupled to the selected core, to thereby provide signals on said set of output lines according to the output code.

2. Apparatus for converting combinations of input signals representing information in one of a plurality of input codes to combinations of output signals representing information in a common output code, comprising: a set of input lines; a set of output lines; a matrix of cores of magnetic material having substantially rectangular hysteresis loop characteristics; Ka set of sense lines inductively coupled to each of said cores; decoding means responsive to signals on the input lines for selecting cores of said matrix to be driven to the opposite magnetic polarity; a first plurality of switches settable in accordance with the input code being sensed to control the connection arrangement of the input lines to said decoding means; a plurality of amplifying means each having an output connected to an output line; and a second plurality of switches settable in accordance with the input code being sensed to control the connection arrangement of the selected sense lines to said amplifying means.

3. Apparatus for converting characters each represented by combinations of signals in any one of a plurality of input codes received over a plurality of input conductors, into a common output code represented by different combinations of signals on a plurality of output conductors, comprising: a plurality of bistable magnetic elements; a decoding network including driving means interconnecting said elements and said input conductors in a predetermined manner for effecting the selection of only one of said elements according to the particular combination of signals received over said input conductors, and for driving the selected element to its opposite magnetic state; a plurality of separate sets of sense lines, one set for each of said plurality of input codes, and each set having a sense line corresponding to each output conductor, and predetermined ones of one or more sets thereof being inductively coupled to each element according to the number of characters represented by the element, said predetermined ones of each set being connected to those corresponding output conductors as required to represent in the output code, the character represented by the magnetic element selected; and selecting means for selecting only those predetermined ones of that set of the plurality of separate sets of sense lines corresponding to the input code in which the input character is represented to produce signals on those output conductors corresponding only to the predetermined sense lines of the selected set.

4. Apparatus for converting combinations of signals representing characters in any one of a plurality of input codes received over a plurality of input conductors to combinations of output signals representing characters in a common output code supplied on a plurality of output conductors comprising: a plurality of 4bistable magnetic elements arrayed in columns and rows;V a decoding network including a plurality of column drive elements responsive to signals on certain of the input conductors, and a plurality of row drive elements responsive to signals on the remainder of the input conductors for effecting the selection of any one of the elements and for driving the selected element to its opposite magnetic state; means operative to control the response of said decoding network to signals on said input conductors in accordance with the particular input code to be converted; a separate set of sense lines for each input code and each set having a sense line corresponding to each output conductor, and predetermined ones of one or more sets thereof being inductively coupled to each element according to the number of characters represented by the element; amplifying means for connecting predetermined ones of each set of sense lines to those corresponding output conductors as required to represent in the output code, the character represented by the magnetic element selected; and selecting means for selecting only those predetermined ones of that set of sense lines corresponding to the input code in which the input character is represented to supply signals on those output conductors corresponding only to the predetermined sense lines of the selected set.

5. Apparatus for converting characters each represented by combinations of signals in any one of a plurality of input codes received over a plurality of input conductors, into a common output code represented by different combinations of signals on a plurality of output conductors, comprising: a plurality of bistable magnetic elements arranged in columns and rows; a decoding network including a plurality of column drive elements responsive to signals on certain of the input conductors, and a plurality of row drive elements responsive to the signals on the remainder of the input conductors for effecting the selection of any one of the bistable magnetic elements, and for driving the selected element to its opposite magnetic state; means operative to control the response of said decoding network to signals on said input conductors in accordance with the particular input code to be converted; a separate set of sense lines for each input code and each set having a sense line corresponding to each output conductor, and predetermined ones of one Or more sets thereof being inductively coupled to each element according 4to the characters represented by the element; a plurality of amplifier devices, one for each of the output conductors, and each comprising a plurality of sensing elements, one for each of the input codes; and a plurality of switch members selectively actuable to select corresponding sensing elements of each of the amplifier devices according to the input code in which the input character is represented whereby, for any selected magnetic element, the predetermined sense lines of the set corresponding to the input code and inductively coupled to the selected magnetic element are connected via the selected sensing elements of the amplifier devices corresponding to the predetermined sense `lines to produce high potential signals on the output conductors corresponding to the predetermined sense lines of that set.

6. Apparatus for converting characters each represented by combinations of signals in any one of a plurality of input codes received over a plurality of input conductors, into a common output code represented by different combinations of signals on a plurality of output conductors, comprising: a coordinate assembly of bistable magnetic elements; a decoding network including a plurality of column drive elements responsive to si-gnals on certain of the input conductors, and a plurality of row drive elements responsive to the signals on the remainder of the input conductors; a first plurality of switch members selectively actuable to connect certain of said input conductors to predetermined column and row drive elements for effecting the selection of one of the bistable magnetic elements, and for driving the selected element to its opposite magnetic state; a separate set of sense lines for each input code and each set having a sense line corresponding to each output conductor, and predetermined ones or one or more sets thereof being inductively coupled to each bistable magnetic element according to the number of characters represented by the element; a plurality of arnplier devices, one for each of the output conductors, and

- each comprising a plurality of sensing elements, one for each of the input codes; and a second plurality of switch members selectively actuable to select corresponding sensing elements of each of the amplifier devices according to the input code in which the input character is represented, whereby, for any selected magnetic element, the predetermined sense lines of the set corresponding to the input code and inductively coupled to the selected magnetic element are connected via the selected sensing elements of the amplifier devices corresponding to the predetermined sense lines to produce high potential signals on the output conductors corresponding to the predetermined sense lines of that set.

7. Apparatus according to claim 6 wherein each said ampliiier device includes a delay circuit, a normally conductive output transistor, and a plurality of amplifier transistors, one of the latter for each input code, each amplifier transistor having the emitter thereof connected to a low potential source via one of the second plurality of switch members, lthe base or each amplitier transistor being connected to the corresponding sense line of a diferent set of lines, the collectors of each amplifier transistor being connected via said delay circuit to a high potential source, and the output of each said delay circuit being connected via said normally conductive output transistor to the corresponding output conductor whereby a signal, on a sense line connected to the base of any one of the amplifier transistors as a result of a magnetic element to which the sense line is inductively coupled, changing to its opposite magnetic state, is delayed in the respective delay circuit so as to produce a pulse on the corresponding output conductor, of a predetermined time duration,

8. Apparatus according to claim 6, including a bistable device having a pair of outputs; a pair of said column drive elements in said decoding network being connected, one to each of the outputs of said bistable device and responsive to a low potential on one or the other of said outputs to respectively energize a first or second group of column drive lines passing through character magnetic elements in said coordinate assembly representing upper and lower shift input characters respectively; a magnetic element in said coordinate assembly representing an upper shift selection character; a magnetic element in said coordinate assembly representing a lower shift selection character; one of said shift selection magnetic elements being selected in accordance with the response of said decoding network to the code signals on the input conductors representing a shift selection character and a clock signal; one or more sense lines passing through each the shift selection magnetic elements according to the number of input codes to which each said shift selection magnetic elements are responsive; the sense lines of each shift selection magnetic element being connected to a separate amplifier device, a delay circuit for said clock signal, and each said amplifier device producing an output therefrom when a shift selection magnetic eiement connected thereto is selected, said output from said amplifier device together with the delayed clock signal forming inputs for said bistable state device whereby a low potential is produced on `one or other of the outputs thereof to select one or other of said groups of column drive lines to determine whether character magnetic elements representing upper or lower shift input characters are selected for decoding the input code to lower and upper case characters respectively on the output code.

References Cited in the iile of this patent UNITED STATES PATENTS 2,518,022 Keister Aug. 8, 1950 2,733,860 Rajchman Feb. 7, 1956 2,835,828 Vogelsong May 20, 1958 2,843,838 Abbott July 15, 1958 2,905,934 Flint Sept. 22, 1959 2,912,679 Bonorden Nov. 10, 1959 

